1. Field of the Invention
This invention relates to a power supply device and, more particularly, to a power sequence apparatus and a driving method for controlling a power sequence with ease and preventing the malfunction of a driver IC.
2. Description of the Related Art
A liquid crystal display (LCD) of an active matrix system uses thin film transistors (TFTs) as switching devices to display a moving picture. Since such an LCD can be made into a device small in size compared to the existing Brown tubes, it has been widely used in a monitor of a personal computer or a notebook computer, in an office automation equipment such as a copy machine, etc. and in a portable equipment such as a cellular phone and a pager, etc.
Referring to FIG. 1, a conventional liquid crystal display includes a data driver 4 for driving data lines DL on a liquid crystal display panel 2, a gate driver 6 for driving gate lines GL on the liquid crystal display panel 2, a timing controller 8 for supplying control signals, data signals and scan signals to the data driver 4 and the gate driver 6, and a power block 10 for supplying a driving voltage to the gate driver 10 through output lines 10a and 10b. 
The liquid crystal display panel 2 displays a picture corresponding to a video signal similar to a television signal through pixels 11 that are arranged at each intersection of the data lines DL and the gate lines GL. Each of the pixels 11 includes a liquid crystal cell controlling the amount of a transmitted light in accordance with the voltage level of the data signal from the corresponding data line DL. A plurality of TFTs are arranged at the intersections of the gate lines GL and the data lines DL, and respond to the scan signal (gate pulse) from the gate line GL to switch the data signal to be transmitted to the corresponding liquid crystal cell.
The timing controller 8 receives a driving voltage from a system main board (not shown). The timing controller 8 supplies video data (R, G and B Data) and the control signals (e.g., input clock, horizontal synchronization signal, data enable signal, etc.) inputted from an interface (not shown), to the data driver 4 including a plurality of drive ICs and to the gate driver 6 including a plurality of gate drive ICs.
The data driver 4 selects a reference gamma voltage corresponding to the video data (R, G and B Data) inputted from the timing controller 8, converts it to an analog video signal, and supplies the analog video signal to the liquid crystal display panel 2.
The gate driver 6 controls line by line the on/off state of the gate terminals of the TFTs arranged on the liquid crystal display panel 2 in accordance with the control signals inputted from the timing controller 8, and applies the analog video signals received from the data driver 4 to each of the pixels 11 connected to each of the TFTs.
The power block 10 receives driving power from a system main board (not shown) and generates a driving voltage for driving the gate driver 6. Particularly, the power block 10 generates a gate high voltage VGH and a gate low voltage VGL of the scanning signal and supplies them to the gate driver 6, upon the generation of a gate scanning clock signal GSC.
The gate low voltage VGL is generated from the power block 10 and directly transmitted to the gate driver 6. On the other hand, the gate high voltage VGH is supplied to the gate driver 6 after the sequence control circuit 12 disposed between the power block 10 and the gate driver 6 controls the point of its output time by delaying the output of the gate high voltage VGH to the gate driver 6 for a predetermined time. Particularly, when a main power VDD is supplied to the power block 10, the gate low voltage VGL and the gate high voltage VGH are simultaneously output from the power block 10 as shown in FIG. 2. However, because the point of the driving time is not synchronized in the gate driver 6, a malfunction occurs if it receives the gate low voltage VGL and the gate high voltage VGH simultaneously. To address this concern, the output of the gate high voltage VGH is delayed for a time period T through the sequence control circuit 12 so that the gate driver 6 receives the gate low voltage VGL first and then the gate high voltage VGH.
Referring to FIG. 3, the sequence control circuit 12 includes an integrator consisting of a resistor R and a capacitor C between the gate driver 6 and the output line 10b of the gate high voltage VGH of the power block 10.
The resistor R and the capacitor C are disposed between the power block 10 and a ground voltage source GND. Such an integrator delays the point of the output time of the gate high voltage VGH from the power block 10 for as much as a time period ‘T’. In other words, the integrator plays a role of simply delaying the gate high voltage VGH for a predetermined time.
As described above, when the main power VDD is supplied to the power block 10, the power block 10 outputs the gate low voltage VGL, and the gate high voltage VGH that is delayed as much as the time T compared to the gate low voltage VGL. But, when the main power VDD is removed once it has been applied to the power block 10, the electric potential at the output line 10b of the gate high voltage VGH becomes high so that the voltage charged at the capacitor C is discharged slowly. At this moment, when the main power is supplied again, the voltage, yet to be discharged completely, and the voltage currently supplied are added together such that a gate high voltage VGH is supplied to the gate driver 6 before the gate driver 6 receives the gate low voltage VGL. This causes malfunctions in the gate driver 6.